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rev.d information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a ad834 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700www.analog.com fax: 781/326-8703 ? analog devices, inc., 2002 500 mhz four-quadrant multiplier features dc to >500 mhz operation differential 1 v full-scale inputs differential 4 ma full-scale output current low distortion ( 0.05% for 0 dbm input) supply voltages from 4 v to 9 v low power (280 mw typical at v s = 5 v) applications high-speed real time computation wideband modulation and gain control signal correlation and rf power measurement voltage controlled filters and oscillators linear keyers for high resolution television wideband true rms functional block diagram 87 65 12 34 current amplifier (w) 4ma fs 8.5ma 8.5ma ad834 v/i v/i x-distortion cancellation y-distortion cancellation w1 +v s x1 x2 w2 ?v s y2 y1 multiplier core general description the ad834 is a monolithic, laser-trimmed four-quadrant analog multiplier intended for use in high-frequency applications, with a transconductance bandwidth (r l = 50 w ) in excess of 500 mhz from either of the differential voltage inputs. in multiplier modes, the typical total full-scale error is 0.5%, dependent on the appli- cation mode and the external circuitry. performance is relatively insensitive to temperature and supply variations, due to the use of stable biasing based on a band gap reference generator and other design features. to preserve the full bandwidth potential of the high-speed bipolar process used to fabricate the ad834, the outputs appear as a differential pair of currents at open collectors. to provide a single-ended ground referenced voltage output, some form of external current to voltage conversion is needed. this may take the form of a wideband transformer, balun, or active circuitry such as an op amp. in some applications (such as power mea- su rem en t) the subsequent signal processing may not need to have high bandwidth. the transfer function is accurately trimmed such that when x = y = 1 v, the differential output is 4 ma. this absolute calibration allows the outputs of two or more ad834s to be summed with precisely equal weighting, independent of the accuracy of the load circuit. the ad834j is specified for use over the commercial temperature range of 0 c to 70 c and is available in an 8-lead dip package and an 8-lead plastic soic package. ad834a is available in cerdip and 8-lead plastic soic packages for operation over the industrial temperature range of ?0 c to +85 c. the ad834s/ d883b is specified for operation over the military temperature range of ?5 c to +125 c and is available in the 8-lead cerdip package. s-grade chips are also available. two application notes featuring the ad834 (an-212 and an-216) ca n now be obtained by calling 1-800-analog-d. for additional applications circuits consult the ad811 data sheet. product highlights l. the ad834 combines high static accuracy (low input and output offsets and accurate scale factor) with very high band- width. as a four-quadrant multiplier or squarer, the response extends from dc to an upper frequency limited mainly by packaging and external board layout considerations. a large signal bandwidth of over 500 mhz is attainable under opti- mum conditions. 2. the ad834 can be used in many high-speed nonlinear operations, such as square rooting, analog division, vector addition, and rms-to-dc conversion. in these modes, the bandwidth is limited by the external active components. 3. special design techniques result in low distortion levels (better than ?0 db on either input) at high frequencies and low signal feedthrough (typically ?5 db up to 20 mhz). 4. the ad834 exhibits low differential phase error over the input range?ypically 0.08 at 5 mhz and 0.8 at 50 mhz. the large signal transient response is free from overshoot and has an intrinsic rise time of 500 ps, typically settling to within 1% in under 5 ns. 5. the nonloading, high impedance, differential inputs simplify the application of the ad834.
rev. d ?2? ad834especifications (t a = 25 c and v s = 5 v, unless otherwise noted; dbm assumes 50 load.) ad834j ad834a/ad834s parameters conditions min typ max min typ max unit multiplier performance transfer function w = xy (1 v ) 2 4 ma w = xy (1 v ) 2 4 ma total error 1 ? v x, y < +1 v 0.5 2 0.5 2 % fs vs. temperature t min to t max 1.5 3 % fs vs. supplies 2 4 v to 6 v 0.1 0.3 0.1 0.3 % fs/v linearity 3 0.5 1 0.5 1 % fs bandwidth 4 500 500 mhz feedthrough, x x = 1 v, y = nulled 0.2 0.3 0.2 0.3 % fs feedthrough, y x = nulled, y = 1 v 0.1 0.2 0.1 0.2 % fs ac feedthrough, x 5 x = 0 dbm, y = nulled f = 10 mhz e65 e65 db f = 100 mhz e50 e50 db ac feedthrough, y 5 x = nulled, y = 0 dbm f = 10 mhz e70 e70 db f = 100 mhz e50 e50 db inputs (x1, x2, y1, y2) full-scale range differential 1 1v clipping level differential 1.1 1.3 1.1 1.3 v input resistance differential 25 25 k w offset voltage 0.5 3 0.5 3 mv vs. temperature t min to t max 10 10 m v/ 4 v to 6 v 100 300 100 300 m v/v bias current 45 45 m a common-mode rejection f 100 khz; 1 v p-p 70 70 db nonlinearity, x y = 1 v; x = 1 v 0.2 0.5 0.2 0.5 % fs nonlinearity, y x = 1 v; y = 1 v 0.1 0.3 0.1 0.3 % fs distortion, x x = 0 dbm, y = 1 v f = 10 mhz e60 e60 db f = 100 mhz e44 e44 db distortion, y x = 1 v, y = 0 dbm f = 10 mhz e65 e65 db f = 100 mhz e50 e50 db outputs (w1, w2) zero signal current each output 8.5 8.5 ma differential offset x = 0, y = 0 20 60 20 60 m a vs. temperature t min to t max 40 40 na/ m a scaling current differential 3.96 4 4.04 3.96 4 4.04 ma output compliance 4.75 9 4.75 9 v noise spectral density f = 10 hz to 1 mhz 16 16 nv/ hz w l oad power supplies operating range 4 9 4 9v quiescent current 6 t min to t max +v s 11 14 11 14 ma ev s 28 35 28 35 ma
rev. d ?3? ad834 ad834j ad834a/ad834s parameters conditions min typ max min typ max unit temperature range operating, rated performance commercial (0 10 khz. 3 linearity is defined as residual error after compensating for input offset voltage, output offset current, and scaling current errors. 4 bandwidth is guaranteed when configured in squarer mode. see figure 5. 5 sine input; relative to full-scale output; zero input port nulled; represents feedthrough of the fundamental. 6 negative supply current is equal to the sum of positive supply current, the signal currents into each output, w1 and w2, and th e input bias currents. specifications in boldface are tested on all production units at final electrical test. results from those tests are used to ca lculate outgoing quality levels. specifications subject to change without notice.
rev. d ad834 ?4? absolute maximum ratings * supply voltage (+v s to ev s ) . . . . . . . . . . . . . . . . . . . . . . 18 v internal power dissipation . . . . . . . . . . . . . . . . . . . . 500 mw input voltages (x1, x2, y1, y2) . . . . . . . . . . . . . . . . . . . +v s operating temperature range ad834j . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 adi 1987 usa a834 pmd y1 y2 ?v s w2 w1 +v s x1 x2 8 7 6 5 4 3 2 1 0.054 (1.37) 0.054 (1.37)
rev. d ?5? t ypical performance characteristicsead834 frequency ? mhz mean output voltage ? mv 1000 1 800 600 400 200 100 80 60 40 20 10 10 100 1000 tpc 1. mean-square output vs. frequency tpc 1 is a plot of the mean-square output versus frequency for the test circuit of figure 2. note that the rising response is due to package resonances. for frequencies above 1 mhz, ac feedthrough is dominated by static nonlinearities in the transfer function and the finite offset voltages. the offset voltages cause a small fraction of the funda- mental to appear at the output, and can be nulled out. see tpc 2. thd data represented in tpc 3 is dominated by the second harmonic, and is generated with 0 dbm input on the ac input and 1 v on the dc input. for a given amplitude on the ac input, thd is relatively insensitive to changes in the dc input amplitude. varying the ac input amplitude while m aint aining a constant dc input amplitude will affect thd performance. wa vetek 2500a signal generator low-pass filter hp3362a signal generator a/b switch da ta precision 8200 vo ltag e c a l ibrator ch1 ch2 hp 54121a sampling heads ab hp54120a digitizing mainframe hp330 computer subtract ch1?ch2 1024 point fft ad834 x y w1 w2 figure 1. test configuration for measuring ac feedthrough and total harmonic distortion the squarer configuration shown in figure 2 is used to deter- mine wideband performance because it eliminates the need for (and the response uncertainties of) a wideband measurement device at the output. the wideband output of a squarer configu- ration is a fluctuating current at twice the input frequency with a mean value proportional to the square of the input amplitude. by placing capacitors c3/c5 and c4/c6 across load resistors r1 and r2, a simple low-pass filter is formed, and the mean-square value is extracted. the mean-square response can be measured using a dvm connected across r1 and r2. sma from hp8656a signal generator sma to hp436a power meter c3 560pf r1 49.9 c5 0.1 f c4 560pf c6 0.1 f r2 49.9 8 765 1234 x2 x1 +v s w1 y1 y2 ?v s w2 ad834 to hp3456a dvm +5v ?5v c1 0.1 f c2 0.1 f r4 75 r3 10 l1 1 h denotes a short direct connection to the ground plane figure 2. bandwidth test circuit 8 765 1234 x2 x1 +v s w1 y1 y2 ?v s w2 ad834 1k a1 ?15v +15v 0.1 f ad707 1k 0.1 f 1k a2 ?15v +15v 0.1 f ad707 1k 0.1 f + +5v 0.1 f 0.1 f ?5v ? v out x y notes r1, r2 should be precision type resistor ( 0.1%). absolute value errors of r1, r2 will cause a scale factor error. r1, r2 mismatches will be expressed as linearity errors. v out = i w1 r1 ? u w2 r2 (if r1 = r2, v out = >i w r1). i w2 i w1 figure 3. low-frequency test circuit frequency ? mhz ac feedthrough ? db 0 1 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 10 100 1000 y feedthrough x feedthrough tpc 2. ac feedthrough vs. frequency frequency ? hz to ta l harmonic distortion ? dbc 0 1m ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 10m 100m 1g y harmonic distortion x harmonic distortion tpc 3. total harmonic distortion vs. frequency
rev. d ad834 ?6? basic operation figure 4 is a functional equivalent of the ad834. there are three differential signal interfaces: the voltage inputs x = x1ex2 and y = y1ey2, and the current output, w, which flows in the direction shown when x and y are positive. the outputs w1 and w2 each have a standing current of typically 8.5 ma. 87 65 12 34 current amplifier (w) 4ma fs 8.5ma 8.5ma ad834 v/i v/i x-distortion cancellation y-distortion cancellation w1 +v s x1 x2 w2 ?v s y2 y1 multiplier core figure 4. functional block diagram the input voltages are first converted to differential currents that drive the translinear core. the equivalent resistance of the voltage-to-current (v-i) converters is about 285 w . this low value results in low input related noise and drift. however, the low full-scale input voltage results in relatively high nonlinearity in the v-i converters. this is significantly reduced by the use of distortion cancellation circuits, which operate by kelvin sensing the voltages generated in the core?an important feature of the ad834. the current mode output of the core is amplified by a special cascode stage that provides a current gain of nominally 1.6, trimmed during manufacture to set up the full-scale output current of 4 ma. this output appears at a pair of open collectors that must be supplied with a voltage slightly above the voltage on pin 6. as shown in figure 5, this can be arranged by inserting a resistor in series with the supply to this pin and taking the load resistors to the full supply. with r3 = 60 w , the voltage drop across it is about 600 mv. using two 50 w load resistors, the full-scale differential output voltage is 400 mv. the full bandwidth potential of the ad834 can be realized only when very careful attention is paid to grounding and decoupling. the device must be mounted close to a high quality ground plane and all lead lengths must be extremely short, in keeping with uhf circuit layout practice. in fact, the ad834 shows useful response to well beyond 1 ghz, and the actual upper frequency in a typical application will usually be determined by the care with which the layout is effected. note that r4 (in series with the ev s supply) carries about 30 ma and thus introduces a voltage drop of about 150 mv. it is made large enough to reduce the q of the resonant circuit formed by the supply lead and the decoupling capacitor. slightly larger values can be u sed, par- ticularly when using higher supply voltages. alternatively, lossy rf chokes or ferrite beads on the supply leads may be used. figure 5 shows the use of optional termination resistors at the inputs. note that although the resistive component of the input 8 765 1234 x2 x1 +v s w1 y1 y2 ?v s w2 ad834 x-input 1v fs optional termination resistor y-input 1v fs optional termination resistor r3 62 r1 49.9 r2 49.9 +5v 1 f ceramic r4 4.7 ?5v w output 400mv fs 1 f ceramic figure 5. basic connections for wideband operation impedance is quite high (about 25 k w ), the input bias current of typically 45 m a can generate significant offset voltages if not compensated. for example, with a source and termination resistance of 50 w (net source of 25 w ) the offset would be 25 w 45 m a = 1.125 mv. this can be almost fully cancelled by including (in this example) another 25 w resistor in series with the unused input (in figure 5, either x1 or y2). to minimize crosstalk, the input pins closest to the output (x1 and y2) should be grounded; the effect is merely to reverse the phase of the x input and thus alter the polarity of the output. transfer function the output current w is the linear product of input voltages x and y divided by (1 v) 2 and multiplied by the scaling current of 4 ma: w = xy 1 v () 2 4 ma provided that it is understood that the inputs are specified in volts, a simplified expression can be used: w = ( xy )4 ma alternatively, the full transfer function can be written: w = xy 1 v 1 250 w when both inputs are driven to their clipping level of about 1.3 v, the peak output current is roughly doubled to 8 ma, but distortion levels will then be very high. transformer coupling in many high-frequency applications where baseband operation is not required at either inputs or output, transformer coupling can be used. figure 6 shows the use of a center-tapped output transformer, which provides the necessary dc load condition at the outputs w1 and w2 and is designed to match into the desired load impedance by appropriate choice of turns ratio. the specific choice of the transformer design will depend entirely on the application. transformers may also be used at the inputs. center-tapped transformers can reduce high frequency distor- tion and lower hf feedthrough by driving the inputs with balanced signals.
rev. d ad834 ?7? 8 765 1234 x2 x1 +v s w1 y1 y2 ?v s w2 ad834 x-input 1v fs optional termination resistor y-input 1v fs optional termination resistor 1 f ceramic 49.9 +5v 4.7 ?5v load 1 f ceramic figure 6. transformer-coupled output a particularly effective type of transformer is the balun * , which is a short length of transmission line wound on to a toroidal ferrite core. figure 7 shows this arrangement used to convert the bal(anced) output to an un(balanced) one (hence the use of the term). although the symbol used is identical to that for a transformer, the mode of operation is quite different. in the first place, the load should now be equal to the characteristic imped- ance of the line (although this will usually not be critical for short line lengths). the collector load resistors r c may also be chosen to reverse terminate the line, but again this will only be necessary when an electrically long line is used. in most cases, r c will be made as large as the dc conditions allow to minimize power loss to the load. the line may be a miniature coaxial cable or a twisted pair. 8 765 1234 x2 x1 +v s w1 y1 y2 ?v s w2 ad834 x-input 1v fs optional termination resistor y-input 1v fs optional termination resistor 1 f ceramic 1.5r c +5v 1 f ceramic 4.7 ?5v r l r c r c output balu n see text c c figure 7. using a balun at the output it is important to note that the upper bandwidth limit of the balun is determined only by the quality of the transmission line; hence, it will usually exceed that of the multiplier. this is unlike a conventional transformer where the signal is conveyed as a flux in a magnetic core and is limited by core losses and leakage inductance. the lower limit on bandwidth is determined by the series inductance of the line, taken as a whole, and the load resista nce (if the blocking capacitors c are sufficiently large). in pra ctice, a balun can provide excellent differential- to-single-sided conversion over much wider bandwidths than a transformer. * for a good treatment of baluns, see ?ransmission line transformers?by jerry sevick; american radio relay league publication. wideband multiplier connections where operation down to dc and a ground-based output are necessary, the configuration shown in figure 8 can be used. the element values were chosen in this example to result in a full-scale output of 1 v at the load, so the overall multiplier transfer function is w = (x 1 ?x 2 )(y 1 ?y 2 ) where it is understood that the inputs and output are in volts. the polarity of the output can be reversed simply by reversing either the x or y input. 8 765 1234 x2 x1 +v s w1 y1 y2 ?v s w2 ad834 49.9 0.1 f +5v 0.1 f 4.7 ?5v 49.9 x 1v y 1v 0.01 f 3.01k 49.9 49.9 167 0.01 f 3.01k + ? ad5539 2.7 261 261 1 f 3.74k 3.74k 1 f 2.7 90.9 49.9 load 49.9 figure 8. sideband dc-coupled multiplier the op amp should be chosen to support the desired output bandwidth. the ad5539 is shown here, providing an overall system bandwidth of 100 mhz. many other choices are possible where lower post multiplication bandwidths are acceptable. the level shifting network places the input nodes of the op amp to within a few hundred millivolts of ground using the recommended balanced supplies. the output offset may be nulled by including a 100 w trim pot between each of the lower pair of resistors (3.74 k w ) and the negative supply. the pulse response for this circuit is shown in figure 9; the x input was a pulse of 0 v to 1 v and the y input was 1 v dc. the transition times at the output are about 4 ns. 10 0% 100 90 10ns 200mv figure 9. pulse response for the circuit of figure 8
rev. d ad834 ?8? power measurement (mean square and rms) the ad834 is well-suited to measurement of average power in high-frequency applications, connected either as a multiplier for the determination of the v i product, or as a squarer for use with a single input. in these applications, the multiplier is followed by a low-pass filter to extract the long-term average value. where the bandwidth extends to several hundred megahertz, the first pole of this filter should be formed by grounded capacitors placed directly at the output pins w1 and w2. this pole can be at a few kilohertz. the effective multiplication or squaring bandwidth is then limited solely by the ad834, since the following active circuitry is required to process only low-frequency signals. (refer to figure 2 test circuit.) using the device as a squarer, the wideband output in response to a sinusoidal stimulus is a raised cosine: sin 2 w t = (1 ? cos 2 w t )/2 recall here that the full-scale output current (when full-scale input voltages of 1 v are applied to both x and y) is 4 ma. in a 50 w system, a sinusoid power of +10 dbm has a peak value of 1 v. thus, at this drive level the peak output voltage across the differential 50 w load in the absence of the filter capacitors would be 400 mv (that is, 4 ma 50 w 2), whereas the average value of the raised cosine is only 200 mv. the averaging con- figuration is useful in evaluating the bandwidth of the ad834, since a dc voltage is easier to measure than a wideband differential output. in fact, the squaring mode is an even more critical test than the direct measurement of the bandwidth of either channel taken independently (with a dc input on the nonsignal channel), because the phase relationship between the two channels also affects the average output. for example, a time delay difference of only 250 ps between the x and y channels would result in zero output when the input frequency is 1 ghz, at which frequency the phase angle is 90 degrees and the intrinsic prod- uct is now between a sine and cosine function, which has zero average value. the physical construction of the circuitry around the ic is critical to realizing the bandwidth potential of the device. the input is s upplied from an hp8656a signal generator (100 khz to 990 mhz) via an sma connector and terminated by an hp436a power meter using an hp8482a sensor head connected via a sec ond sma connector. since neither the generator nor th e sensor provide a dc path to ground, a lossy 1 m h inductor l1, formed by a 22-gauge wire passing through a ferrite bead (fair-r ite type 2743001112) is included. this provides adequate im pedance down to about 30 mhz. the ic socket is mounted on a ground plane with a clear area in the rectangle formed by the pins. this is important since significant transformer action can arise if the pins pass through individual holes in the board; it has been seen to cause an oscillation at 1.3 ghz in improperly constructed test jigs. the filter capacitors must be connected directly to the same point on the ground plane via the shortest possible leads. parallel combinations of large and small capaci- t ors are used to minimize the impedance over the full frequency range. refer to tpc 1 for mean-square response for the ad834 in cerdip package, using the configuration of figure 2. to provide a square root response and thus generate the rms value at the output, a second ad834, also connected as a squarer, can be used as shown in figure 10. note that an attenuator is inserted both in the signal input and in the feed- back path to the second ad834. this increases the maximum input capability to +15 dbm and improves the response flatness by damping some of the resonances. the overall gain is unity; that is, the output voltage is exactly equal to the rms value of the input signal. the offset potentiometer at the ad834 out- puts extends the dynamic range and is adjusted for a dc output of 1 25.7 mv when a 1 mhz sinusoidal input at e5 dbm is app lied. additional filtering is provided; the time constants were chosen to allow operation down to frequencies as low as 1 khz and to provide a critically damped envelope response, which settles typically within 10 ms for a full-scale input (and proportionally slower for smaller inputs). the 5 m f and 0.1 m f capacitors may be scaled down to reduce response time if accurate rms opera tion at low frequencies is not required. the output op amp must be specified to accept a common-mode input near its supply. note that the output polarity may be inverted by replacing the npn transistor with a pnp type. ad301 ? + 33pf 0.1 f 0.1 f 15k 10k 47.5k 8 765 1234 x2 x1 +v s w1 y1 y2 ?v s w2 ad834 8 765 1234 x2 x1 +v s w1 y1 y2 ?v s w2 ad834 24.91 49.9k 1 f 100 100 49.9 49.9 49.9 49.9 input 24.9 1 f 5 f 5 f 100 100 15k +5v 75 ?5v 2n3904 output 10 figure 10. connections for wideband rms measurement
rev. d ad834 ?9? frequency doubler figure 11 shows another squaring application. in this case, the output filter has been removed and the wideband differential o utput is converted to a single-sided signal using a balun, which consists of a length of 50 w coax cable fed through a ferrite core (fair-rite type 2677006301). no attempt is made to reverse terminate the output. higher load power c oul d be achieved by replacing the 50 w load resistors with ferrite bead inductors. the same precautions should be observed sma from hp8656a generator sma to hp8568a spectrum analyzer 8 765 1234 x2 x1 +v s w1 y1 y2 ?v s w2 ad834 1 h 75 0.1 f 49.9 49.9 560pf 0.1 f 560pf 0.1 f balu n +5v 10 0.1 f ?5v figure 11. frequency doubler connections with regard to pc board layout as recommended above. the output spectrum shown in figure 12 is for an input power of +10 dbm at a frequency of 200 mhz. the second harmonic component at 400 mhz has an output power of e15 dbm. some feedthrough of the fundamental occurs: it is 15 db below the main output. it is believed that improvements in the de sign of the balun w ould reduce this feedthrough. a spurious output at 600 mhz is also present, but it is 30 db below the main output. at an input frequency of 100 mhz, the measured power level at 200 mhz is e16 dbm, while the fundamental feedthrough is reduced to 25 db below the main output; at an output of 600 mhz the power is e11 dbm and the third harmonic at 900 mhz is 32 db below the main output. frequency ? mhz ?10 150 output power ? dbm ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 0 200 250 300 350 400 450 500 550 600 650 figure 12. output spectrum for configuration of figure 11 wideband three-signal multiplier/divider two ad834s and a wideband op amp can be connected to make a versatile multiplier/divider having the transfer function w xxyy uu z = - + (e )(e) () 1212 12 with a denominator range of about 100:1. the denominator input u = u1 e u2 must be positive and in the range 100 mv to 10 v; x, y, and z inputs may have either polarity. figure 13 shows a general configuration that may be simplified to suit a particular application. this circuit accepts full-scale input volt- ages of 10 v, and delivers a full-scale output voltage of 10 v. the optional offset trim at the output of the ad834 improves the accuracy for small denominator values. it is adjusted by nulling the output voltage when the x and y inputs are zero and u = 100 mv. the ad840 is internally compensated to be stable without the use of any additional hf compensation. as the input u is reduced, the bandwidth falls because the feedback around the op amp is proportional to the input u. this circuit may be modified in several ways. for example, if the differential input feature is not needed, the unused input can be connected to ground through a single resistor, equal to 8 765 1234 x2 x1 +v s w1 y1 y2 ?v s w2 ad834 100 100 909 909 0.1 f 909 100 100 909 0.1 f 8 765 1234 x2 x1 +v s w1 y1 y2 ?v s w2 ad834 100 100 909 909 0.1 f 909 100 100 909 0.1 f 100 100 20k 10k 75 ad840 (a3) 4.7 0.1 f 0.1 f 4.7 7.5v 7.5v ?15v +15v w 10v x1 x2 y1 y2 u1 u2 z figure 13. wideband three-signal multiplier/divider the parallel sum of the resistors in the attenuator section. the full-scale input levels on x, y, and u can be adapted to any full-scale voltage down to 1 v by altering the attenuator ratios. note, however, that precautions must be taken if the attenuator ratio from the output of a3 back to the second ad834 (a2) is lowered. first, the hf compensation limit of the ad840 may be exceeded if the negative feedback factor is too high. second, if the attenuated output at the ad834 exceeds its clipping level of 1.3 v, feedback control will be lost and the output will suddenly jump to the supply rails. however, with these limi- tations understood, it will be possible to adapt the circuit to smaller full-scale inputs and/or outputs, and for use with lower supply voltages.
rev. d ad834 C10C outline dimensions dimensions shown in inches and (mm). 8-lead plastic dip (n-8) seating plane 0.060 (1.52) 0.015 (0.38) 0.210 (5.33) max 0.022 (0.558) 0.014 (0.356) 0.160 (4.06) 0.115 (2.93) 0.070 (1.77) 0.045 (1.15) 0.130 (3.30) min 8 1 4 5 pin 1 0.280 (7.11) 0.240 (6.10) 0.100 (2.54) bsc 0.430 (10.92) 0.348 (8.84) 0.195 (4.95) 0.115 (2.93) 0.015 (0.381) 0.008 (0.204) 0.325 (8.25) 0.300 (7.62) 8-lead cerdip (q-8) 1 4 85 0.310 (7.874) 0.220 (5.588) pin 1 0.100 (2.540) bsc 15 0 0.345 (8.763) 0.290 (7.366) 0.015 (0.381) 0.008 (0.203) seating plane 0.230 (5.842) max 0.485 (12.319) max 0.015 (0.381) min 0.200 (5.080) 0.115 (2.921) 0.023 (0.584) 0.014 (0.356) 0.070 (1.778) 0.038 (0.965) 0.230 (5.842) max 8-lead soic (r-8) dimensions shown in millimeters and (inches). 0.25 (0.0098) 0.19 (0.0075) 1.27 (0.0500) 0.41 (0.0160) 8 0 0.50 (0.0196) 0.25 (0.0099) 45 85 4 1 5.00 (0.1968) 4.80 (0.1890) pin 1 4.00 (0.1574) 3.80 (0.1497) 1.27 (0.0500) bsc 6.20 (0.2440) 5.80 (0.2284) 1.75 (0.0688) 1.35 (0.0532) seating plane 0.25 (0.0098) 0.10 (0.0040) 0.49 (0.0192) 0.35 (0.0138)
rev. d ad834 ?11? revision history location page data sheet changed from rev. c to rev. d. edits to ordering guide model nomenclature corrected . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
?12? c00894?0?4/02(d) printed in u.s.a.

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